Process Migration And Reinforce Design Of 40nm Standard Cell Library

With the rapid development of the space technology, the control system in spacecraft has an increasing requirement for the performance and reliability of the chip. The standard cell library that is the basis of ASIC design determines the performance and reliability of the chip. In order to ensure quality and reduce cost, process migration was applied to achieve a new standard cell library. In order to reduce the impact of single event effect on the reliability of the chip, we also reinforced the standard cell library. The main works and contributions of the dissertation include:1) On the basis of the needs of semi-custom design, we chose 42 kinds, 3 driving degrees, 132 cells to compose the standard cell library.2) SKILL language belonged to Cadence was used to code the program of process migration. The circuit and layout in the standard cell library was migrated form 65 nm to 40 nm by replacing device, scaling down size of transistor and zooming graphic.3) After the size of PMOS and NMOS had been simulated again and again, the circuit obtained better performance. We optimized active region, through hole, poly gate and metal wire in layout in order to offset the loss which process migration caused of process effect, performance, power, area and routing resource as more as possible.4) With the analysis of mechanism that single event effect happen, we applied the DICE strcture in latch circuit and isolated pair of sensitive nodes in layout so that the sequential cells have a good anti-SEU capability. Muller_C which can effectively inhibit the spread of SET pulse was joined into the input ports of sequential cell. Because the DRC rules and the PCEEL of substrate/well contact was customized, higher LEF is needed to cause SEL.5) The evaluation indicators included delay, setup/hold time, power, area and ability to resist SEU, SET and SEL have been modeled in math and simulated by HSPICE. Compare to XXXX 40 nm standard cell library, we got a conclusion that the library we design greatly enhance ability to resist SEU, SET and SEL with small cost of delay, power and area. We think that the standard cell library meets the expectation according to compromise principle.