Analysis Of Single-event Effect Vulnerability In Standard Cell Library

With the development of integrated circuit technology,reliability of circuit is more seriously threatened by radiation effects.As circuit geometries continue to scale down,circuits are increasingly affected by Single-event effect(SEE).Integrated circuit usually consists of large number of standard cells.The SEE vulnerability of standard cells are basis for the design of radiation hardened integrated circuit.Considering the trade-off between time and accuracy,a simulation approach is used to obtain data of standard cells about SEE.Based on a circuit-level SEE simulation approach,a SEE simulation on the standard cells in the standard cell library has been carried in this work.The effects of feature size,driving capability,and layout structure on SEE vulnerability of standard cells are studied.The main works and contribution of this paper are as follows:(1)Circuit-level simulation method is used to obtain SEE data of 180 and 40 nanometer Inverter(INV).The reduction in feature size leads to a rapid decrease in the area of the sensitive drain region of the INV.Due to the charge sharing effect in the cell,the Single-event transient(SET)pulse of the Inverter is affected by the pulse narrowing effect.Along with the decrease in feature size,a decreasing trend is found in the ratio of SEE cross section to layout area and the SET pulse width of inverter.(2)Six kinds of cells are simulated in this work,which include INV,NOR,NAND,D flip-flop(DFF),OR,AND.The influence of driving capability on SEE vulnerability of the standard cell is studied.Simulation result shows that,with the increase in driving capability,different trend founded in different standard cells.However,when the driving capability is increased to a high multiple,the ratio of the SEE cross-section to the layout area of the standard cell will decrease significantly.With the increase of driving capacity,a downward trend of SET pulse width is founded in most cells.Among all the standard cells for simulation results,the Inverter has the strongest anti-single event effect ability.(3)The influence of sub-module driving capability,transistor connection strategy and the number of metal holes on the SEE vulnerability of standard cells have been studied.The simulation result found that sub-modules with high driving capability have higher anti-single event effect performance than sub-modules with lower driving capability;A common-drain connection strategy of internal transistor helps reduce the area of the drain.Replacing the common source strategy and independent source/drain connection strategy of internal transistors with a common drain connection strategy,which can effectively enhance the anti-single event effect performance of standard cell;Increasing the number of metal contact holes between active area and first layer metal can effectively enhance the anti-single event effect performance of standard cell.