| This thesis presents a fully integrated low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. It uses a novel switched capacitor scheme that raises the control voltage above the supply voltage level, thus increasing the voltage headroom and allowing the low dropout operation of the voltage regulator. The described method allows continuous time operation of the LDO regulator.;Several different circuit topologies to implement this approach are presented; each one of them is properly analyzed and explained. A comparison between the different present topologies as well as with previous reported work is presented.;The regulator is designed using a regular 0.13 mum CMOS process. It is capable of delivering a 1.5 V at a loading of 50 mA with a dropout voltage of 0.1 V, and is stable for a wide load current range with loading capacitances up to 100 pF. The output variation when a full load step is applied is 60 mV and the recovery time is 0.2 mus. The total on-chip capacitance is less than 7 pF which results in an area of less than 0.009 mm2. Additionally, the power consumption is low with a quiescent current of 120 muA. Extensive simulation results demonstrate the feasibility of the proposed design. |
