The Design Of SPI Module And Its AMBA Interface In X-DSP

Digital signal processing technology is constantly developing.Nowadays, DSP chip is highly integrated. There are many methods for data transmission. To meet the project, We have to manage to make different buses interacted. How to make different buses interact efficiently has become a hot point in IC chip design.The subject of this paper comes from an optional project of our institute.This project has developed a DSP chip which has multi-core and multi-bus. Moreover this DSP chip is versatile and expandable. In this paper we designed and implemented this SPI Component in verilog hardware description language. The interface of this DSP chip match with AMBA 3.0 APB bus. We have also designed a bridge between the SPI Component and the Teranet bus.The main work of this thesis contains the following aspects.Firstly, We designed and implemented a SPI Component, This SPI Component works on master or slave by writing in its configurable register. There is advantages in build up, Implemention and multiplexing. In this article we achieved our designing in TOP-DOWN and modular method. This SPI Component is divided into different modules include interrupt module, Interface module, FIFO module, Register module and Transmit/receive module.Secondly. We designed a bridge which can made the AMBA 3.0 APB bus and Teranet configurate bus connected and made their protocol converted. We have designed the trigger and feedback mechanism between the two buses, Which made it competently bridge the two buses.Then, We built the test environment, And established the connecting structure of each modules. The test module writes data into registers of SPI Component through Teranet and bridge module.Make it possible to achieve data transfer in basic SPI master-slave mode, LOOP mode and the 3-pin mode.In order to achieve the basic SPI master-to-slave mode, LOOP mode and 3-pin mode,We have compiled a tester,Which can generate control signal, Address signal and data signal from Teranet. It can also generate configurate signal, Address signal and data exchange between SPI master and slave.Last, We have finished the module-level verification and simulation for SPI basic master-slave mode,LOOP mode and the 3-pin mode.We made a detailed analysis of it. Morever, We have checked the coverage and logic synthesis for SPI Component,moreover we have made a detailed analysis for it. We have achieved design goal we desired.