Soft Core Design Compatible With The MCS-51 Instruction Set

There are lots of microprocessor in embedded design field to choose form such as AVR, PIC, MCS-51, Microchip that used in low-level application and some others used in high-level application such as ARM series and Cortex series. MCS-51 kernel microprocessors now is still widely used. However the work frequency is 1/12 of extern crystal vibration frequency, which is decided by the characteristics of MCS-51 instruction set. MCS-51 instruction set is CISC(Complex Instruction Set Computer), that means bytes of Instruction and the required clock number for executing one piece instruction is not fixed. For the unit with the machine cycle instruction execution time, at least for 12 clock. This clock constraint limits the processing speed of the processor. With the development of intelligent dressing equipment and Internet of things, we more and more demand for high-performance low-power processor. So we hope to be able to increase the speed of the processor.To achieve this goal there are two ways, on the one hand we can improve the speed of the device through the using of advanced technology, on the other hand we can optimize instruction execution efficiency.In this paper, from aspects of optimizing the instruction execution efficiency by introducing two-degree pipeline to improve the efficiency of execution of the instruction set, completing a compatible with MCS-51 instruction set soft core design. The soft core can run Keil compiler of C language program, complete the IO, arithmetic and logic operations, timer and external interruption, serial port communication, and other functions. Implementation of MCS- 51 all functions.The average instruction execution time is 7 clock, reduced by 50% compared the original design. Synplify synthesis results show that the soft core can run the highest clock is 109 MHz. The overall performance and the present market for products has improved significantly. Finish timing simulation with Modelsim and board level validation with FPGA. In the simulation part put forward some automated testing and validation method such as log contrast and memory constrast, which are useful in large scale IC design.