VLSI Architecture Of JPEG2000 Bit-Plane Coding

Image compression techniques are very important for the storage and transmission of the huge data in the modern image processing. Nowadays, the traditional still image compression techniques, e.g., the well-known JPEG standard, could not meet the rapidly increased demand for the high quality low bit-rate images in various emerging applications. The latest still image compression standard JPEG2000 achieves much better coding efficiency and image quality than JPEG standard. With its excellent performance and prominent features, JPEG2000 will no doubt become the main-stream in the image compression field in the future; therefore, high attention is paid to its VLSI realization.This dissertation deeply accessed the hardware implementation techniques for bit-plane coding in JPEG2000.Bit-plane coding is used to encode the code block of quantized discrete wavelet coefficients, which can generate contexts and decisions and make them become inputs of arithmetic coder to complete main encoding work for JPEG2000. Firstly, bit-plane coding algorithm is analyzed and verified by C Language. Secondly, a concrete VLSI architecture is proposed to implement three coding passes of bit-plane coding ( Clean Up Coding Pass, Significant Propagation Coding Pass, Magnitude Refinement Coding Pass ) and four basic coding operations ( Zero Coding, Sign Coding, Magnitude Refinement Coding, Run Length Coding ),which are described by Verilog HDL . Finally, the VLSI architecture of bit-plane coding has been simulated and synthesized. The practical results tested by logic analyzer are identical as simulation results.In the process of Zero Coding, four sub-band data after discrete wavelet transform is separated into two classes. At the same time, Run Length Coding is turned into the process of looking up. These measures enhance encoding efficiency and simplify the circuit architecture of bit-plane coding. The 32 X 32 code block can be encoded efficiently under 50 MHz. This architecture could be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image/video applications.