Design Of Low Power Capacitor-less LDO

In recent years, as the requirement of portable electronic products increasing rapidly, thedemand for the power management chip grows urgently too, which mainly used to improvethe efficiency of the power devices, thereby extending battery life of the equipment. As acommon power management chip, LDO (low dropout regulator) has received a wide range ofapplications for the advantages of simple circuit, low noise and low-power. However, thetraditional LDO has an external capacitor off chip, it increases the PCB (Printed CircuitBoard) area and is difficult to use in SOC (System on Chip) chip. For these considerations, todesign a LDO without external capacitor become the engineer’s goal in industry.There are two main difficult points to design a LDO without external capacitor. First,traditional LDO has a main pole locating at the output node; it takes a left-half-plane zero torealize frequency compensation, which is produced by the external capacitor’s equivalentresistance. For this point, the stability of the Capacitor-Less LDO must be reconsidered.Besides, the traditional LDO can reduce the output voltage overshoot and spikes duringoutput transient dynamics by using the external capacitor to complete the charge anddischarge While the Capacitor-Less LDO, to improve the transient response capability is toincrease the bandwidth of loop, and it will increase power dissipation. Therefore, thecommon way is to design a slew rate enhancement circuitry to increase the slew rate of theerror amplifier during output transient dynamics. It will improve speed of LDO transientresponse; but in normal power supply, the slew rate enhancement circuitry does not work, thisproperty makes it has lower power consumption. In this paper, with the discussion andanalysis of the previous research, new circuit structure of the Capacitor-Less LDO isdesigned.The LDO circuit is used for digital circuits in a low power LDO SIGMA-DELTA ADCand is manufactured base on standard MXIC0.35μm CMOS process, the power supplyvoltage varies2.7V~5.5V. The output voltage is3.3V, and the maximum load current is5mA.The whole circuit is divided into two parts: bandgap and main LDO circuit. Bandgap’sreference source provides an independent reference without temperature and power supply.So the power consumption can be very low, and simulation result shows that the currentconsumption is only12μA. The slew rate enhancement circuitry of the main LDO circuit cangreatly increase the slew rate of the error amplifier during output transient dynamics, so itwill improve the speed of LDO transient response, which also reduces the output voltage spikes and overshoots. Compared with the LDO in other papers, the slew rate enhancementmodule of this LDO has simple structure and good performance. Furthermore, the erroramplifier is biased in the sub-threshold region; it will effectively reduce the powerconsumption of the overall circuit. By using CADENCE simulation, the dropout voltage isless than100mV, the current consumption of the circuit is31μA. The voltage spike is lessthan100mV during the maximum output transient dynamics. The LDO meet the applicationrequirements through various simulations.