Design And Realization Of Data Acquisition System For TOF-SIMS Based On High Speed ADC

The Time-of-Flight Secondary Ion Mass Spectrometer(TOF-SIMS)is one of the most methods for the surface analysis,which combines secondary ion mass spectrometry and time-of-flight mass spectrometry,it has the advantages of fast analysis and high resolution,has been widely used in the fields of geology,biology and environmental science.As a major compoment of TOF-SIMS,the data acquisition system can acquire the ion signals,the acquisition result will directly affect the resolution and the accuracy of the instrument.The paper is based on the “National Major Scientific Instruments and Equipment Development Special Projects”,to design a data acquisition system based on high-speed ADC for TOF-SIMS instruments.Firstly,the paper compares two data acquisition technologies for TOF-SIMS: ADC(Analog-to-Digital Conversion)and TDC(Time-to-Digital Conversion),and according to the need of TOF-SIMS instrument for data acquisition system completed the overall design.Then,based on the overall design of the system,completed the hardware circuit design,FPGA sequential logic design and the driver of acquisition system.The hardware circuit mainly includes broadband differential conditioning circuit and high-speed analog-to-digital conversion circuit.FPGA as the master chip of the acquisition system,provides accurate timing control for the system,including high-speed ADC timing control module,DDR3 SDRAM controller module and PCIE bus control module.The driver of the acquisition system is implemented by the Windriver tool,the drivers include device drivers and PCIE application program.Finally,test the completed TOF-SIMS high-speed data acquisition system,includes: broadband differential conditioning circuit testing,DDR3 SDRAM memory module testing,high-speed ADC dynamic performance testing,PCIE bus transmission speed testing.The test results show that the sampling rate of the acquisition system is 3.2Gsps,and when the collection frequency is 100 MHz sine signal,the effective number of bits is 9.283 bits.DDR3 SDRAM can realize data read and write operations by FPGA control.PCIE bus transmission speed in DMA mode exceeds 1000MB/s.The test results meet design specifications.