Design And Implementation Of High-Speed Camera Recording System

With the rapid development of measurement technology,in order to improve the image quality and measurement accuracy,high-resolution,high frame rate high-speed camera is widely used to shoot experimental phenomena,resulting in high-speed,massive image data,how these high-speed video data Lossless storage becomes an urgent problem to be solved.Aerospace and other military applications more harsh environment,are generally accompanied by high and low temperature,high humidity and strong earthquake,so to meet the performance requirements under the premise of how to design a good environmental characteristics,high-quality,high-speed video storage system,Real-time lossless storage of massive video data is the key to research.In this paper,Eo Sens CL series of high-speed CMOS camera,to overcome the commonly used equipment in the general existence of large volume,data export slow,simple communication interface,control trouble and ease of use and other issues,designed and implemented based on FPGA + Power PC + SSD miniaturized high-speed video real-time recording storage system.In this paper,FPGA as a high-speed data acquisition,data processing and image output display and data upload control center to Power PC architecture processor P1010 as a data storage core processor to SATA interface solid state hard drive as a data storage medium,using Camera Link,PCIe,IIC,RS485 and optical fiber and other means of communication to achieve high-speed camera output 600MB/s video data real-time acquisition and storage,and through the optical interface to achieve high-speed data upload.The main work of the paper is as follows:1.This paper analyzes and studies the realization principle and advantages and disadvantages of the high-speed data acquisition and storage system in the market at present,and puts forward the realization scheme of the system according to the design requirements.The system uses high-speed camera to collect high-speed video and through the Camera Link interface input system to PCIe bus as the system within the high-speed data transmission interface to RS485 as the command transmission interface to fiber as a data upload interface to SSD as a data storage medium,Embedded operating system,and ultimately through the FPGA + Power PC + SSD architecture to meet system requirements.2.Design and implementation of DS90CR288 AMTD differential signal conversion for Camera Link interface video data input.PCIe high-speed data transmission interface is designed and implemented based on Gen2 ×4 width PCIe link through Stratix IV GX embedded PCIe hard core,And designs and realizes the high-speed data transfer DMA controller under the PCIe link.For the instruction transmission interface,the RS485 communication interface of the FPGA is designed and realized,and the LVDS level and the CMOS level conversion are realized by the level conversion chip.3.For high-speed camera output 600MB/s video data,the design and implementation of the 4-way Power PC based on Gen 2 ×1 width of the PCIe link,each way Power PC storage 150MB/s image data and additional information;for PCIe bus,design and implementation PCIe Switch bridge chip on the FPGA PCIe link expansion,and with 4 Road Power PC into a path;for high-speed data upload,design and implementation of the FPGA optical module communication interface,data transfer rate up to 2.125 Gbps.Finally,the performance of the high-speed camera recording and storage system is tested in this paper.The test results show that the indexes meet the technical requirements of the high-speed camera recording system.