High-speed Serial Protocol Triggering And Decoding Function Design

With the rapid development of electronic information technology,the application of high-speed serial bus interface technology has become increasingly widespread and has gradually become the mainstream bus interface technology.The large number of applications of high-speed serial buses has led to an increase in the demand for high-speed serial signals,and the test requirements are more stringent.Only test instruments with high sampling rates,high bandwidth and high memory depth meet these requirements.In the field of electronic information,the most widely used test instrument is a digital oscilloscope.High-end oscilloscopes with high-speed serial protocol triggering and decoding functions are indispensable.Domestic oscilloscopes have been unable to decode high-speed serial protocols due to sampling rate and bandwidth limitations.To this end,the design is based on a high-definition digital oscilloscope platform,focusing on the high-speed serial protocol triggering and decoding functions in the oscilloscope.Based on the existing platform,the hardware scheme of the high-speed serial protocol analysis and decoding function is proposed.The real-time decoding and triggering functions of PCIe1.0 and SATA1.0 high-speed serial protocols are designed and implemented.The program has good compatibility: this scheme is compatible with the original low-speed protocol decoding function of the oscilloscope,and has strong scalability: it can use this scheme to decode more high-speed serial bus protocols.It has reached the domestic leading level in the triggering and decoding of high-speed serial protocols.The main contents of this paper are as follows:1.Research on high-speed serial bus protocol coding specification and data transmission mode: This paper mainly studies the coding specifications and data transmission methods of PCIe1.0 and SATA1.0 high-speed serial protocols,and designs reasonable decoding schemes for different protocols.2.high-speed serial bus protocol codec algorithm principle and implementation method: PCIe1.0 and SATA1.0 two high-speed serial bus protocol encoding and decoding methods are different,the two bus protocol encoding and decoding algorithms are studied separately Finally,the codec is realized by an efficient and fast algorithm.The algorithms involved in the protocol codec include protocol data add/descramble algorithm,parallel 32bit/16 bit CRC check algorithm,8B/10 B codec algorithm,snapshot algorithm,search sampling edge algorithm and frame start matching algorithm.3.High-speed serial protocol triggering and decoding module design: The module is divided into protocol processing,protocol analysis,protocol decoding,protocol triggering and protocol display.The protocol processing module is responsible for restoring the sampled data to the original protocol data after being processed by the edge search,the snapshot,the frame header matching,the 8B/10 B decoding,the descrambling,and the like.The protocol analysis module segments the original protocol data according to the frame structure,then calculates the value of the CRC,and finally sends the data and the CRC check result to the protocol trigger and protocol decoding module.The trigger module generates a trigger signal according to a trigger condition set by the user.The protocol decoding module packages and decodes the decoded data,the trigger flag,the data type,and the start time to the industrial computer.The IPC acts as a protocol display module to display the protocol data packet and protocol waveform on the screen for one decoding.After testing and verifying the high-speed serial protocol triggering and decoding functions designed in this paper,the test results show that the function can get the correct decoding result,real-time decoding and triggering,and can realize the protocol decoding function in deep storage mode.The line protocol triggering and decoding functions are implemented correctly.