Radiation-Hardening Design Based On SMIC's 0.13um CMOS Process

With the rapid development and integration of materials,chemistry,engineering and other disciplines,the minimum size of devices in integrated circuits continues to push the limits.Integrated circuits are the core of aerospace and electronic products.As the size of integrated circuits continues to shrink,the accompanying power supply voltage continues to decrease,the gate oxide thickness reaches several nanometers,and the integration level is high.The radiation hardening design of the circuit also brings obvious changes and more serious challenges.For example,the thickness of the gate oxide layer is very thin,which causes the total dose effect to have a very small impact on the integrated circuit.The reduction of the power supply voltage leads to a significant increase in the single event effect,and the high level of integration leads to serious Multi-bit Upset,led to new and higher requirements for anti-radiation design.Radiation-resistant reinforcement design can be carried out in many aspects,such as the use of new materials,the development of radiation hardening processes,the design of radiation hardening circuit structures,etc.,but the development of new materials and processes costly,low production requirements and other issues.The use of existing mature technology through the circuit design for radiation-resistant reinforcement has the advantages of low cost and good performance,and has become a hot spot of research today.Based on the above reasons,this paper focuses on the single event effect and the method of single event effect circuit reinforcement.The main contents are as follows:Based on the SMIC' 130 nm CMOS process,this model uses the Sentaurus TCAD software to model and parameterize 130 nm NMOS transistors,and then perform single-element device-level simulation,including different LET,different incident angles,and different drain voltages.Through the analysis of the simulation results,the following results are obtained: the single-particle pulse current is linear with the change of LET;the incident angle is also different for the single-particle pulse current,which is related to the structure of the device;under the same LET,single-particle pulse The current increases as the drain voltage increases,becoming a linear relationship.By analyzing the basic theory of single-event effect,it is proposed that for sensitive nodes,reducing the voltage difference between the drain and the substrate can reduce the absorption of unbalanced carriers by the drain,and thus reduce the single-particle pulse current.Subsequent simulations of different LETs after boosting the source and substrate voltages,compared with the simulation results before the substrate voltage was changed,found that the single-event pulse current was significantly reduced after boosting the source and substrate voltage,and The tendency for LET to increase and increase is slowed down.Based on the analysis of the simulation results and the single event effect charge collection theory,a single event effect hardening method is proposed,which is the hardening method of the source lining voltage follow-up output,through the inverter,NAND gate,NAND gate hardening circuit.The simulation demonstrates that this method has a strong ability to resist single-particle effects.