The Research And Design Of Low Dropout Regulator Based On CMOS Technology

With the increasing application of portable consumer electronics products,power management chips have become one of the most concerned issues in the IC industry.Low dropout regulator(LDO)is widely used in various handheld electronic devices and implantable devices due to its low output noise,simple structure and good load regulation ability.With the continuous development of semiconductor technology,the feature size of CMOS process continues to decrease,and the power supply voltage also decreases.These trends make LDO play an irreplaceable role in power management chips.With the continuous development of CMOS technology,LDO is gradually developing towards the trend of high integration,low power consumption,low noise and fast transient response.However,these performance indicators are mutually compromised or restricted.Generally,LDO applied in different scenarios have different emphasis on their performance indicators.In response to this problem,two different types of low dropout regulators with and without off-chip capacitors are designed based on TSMC 0.13?m process in this paper.Firstly,an LDO regulator based on impedance attenuation buffer compensation is studied.Compared with the conventional structure,the LDO can withstand the power supply voltage higher than the process withstand voltage value.The load current range of the proposed LDO circuit is 0-80m A,and 5?F off-chip capacitor is adopted at the load.The simulation results of the circuit are as follows:the low frequency power supply rejection ratio is 67.5 d B,the line regulation is 0.4m V/V,and the load regulation is 0.0093m V/m A.The LDO shows good transient response characteristic,when the load current changes back and forth from 0 to 80 m A,the amplitude of the output voltage's overshoot and undershoot are 3m V and 6m V respectively,and the recovery time is about 0.5?S,the overall layout area of the circuit is 0.08mm~2,and the simulation results show that the LDO meet the design requirements.The LDO without off-chip capacitor adopts a single-ended structure based on the flipped voltage follower,which effectively improves the utilization rate of current.The detailed analysis and design flow of modules such as flipped voltage follower,three-input amplifier and sub-1V bandgap reference circuit are given.It can be seen from the simulation results that the load current range of the realized LDO circuit is100?A-30m A,and the quiescent current of the circuit under full load condition is42.4?A,the low frequency power supply rejection ratio is 38.89d B,and the power supply rejection ratio at 1MHz is 25d B,the line regulation is 15.25 m V/V,and the load regulation is 0.026 m V/m A,when the load current changes back and forth from100?A-30 m A,the amplitude of the output voltage's overshoot and undershoot are 33.3m V and 77.6 m V respectively,the recovery time is about 0.5?S.