Research And Design Of Low-power Extensible Processor In SDR Transceiver Chip

Currently,high-performance transceiver chips mostly use Software Defined Radio(SDR)technology,and use embedded low-power processors to perform complex flow control,filter coefficient configuration,and signal calibration.The SDR transceivers have the characteristics of low hardware overhead and reconfigurable algorithms,and have gradually become the mainstream trend of future development.Considering the power consumption requirements of the SDR transceiver chip and the complicated internal edge computing scenarios,the embedded processor is required to have low power consumption,extensilibity,and certain hardware acceleration capabilities.Aiming at the requirements of the SDR transceiver chip with embedded processor,a extensable,low-power processor based on the RISC-V open source instruction set is researched and designed in this thesis.The main work of this thesis is organized as follows:This thesis adds the standard extension set for integer multiplication and division and the standard extension set for compressed instructions in the base instruction set of RISC-V to implement a three-stage pipeline processor.Through the instruction prefetch mechanism and predecoding structure,the target processor solves the problem of address misalignment which is caused by the interleaving of compressed instructions and 32-bit standard instructions.What's more,the target processor implements a low-power mode to meet the low power consumption requirement of the SDR transceiver chip by using the multi-clock domain shutdown mechanism.Considering the transceiver's requirements for edge computation,a universal extensible processor interface is designed in this thesis and the corresponding extensiable hardware design is implemented as well.The interface helps to extend coprocessors in the standard RISC-V processor core to implement a domain specific architecture.Based on the extensibility design of the processor,a FFT acceleration coprocessor and a convolutional neural network acceleration coprocessor are designed.According to the micro-architecture of the target processor,a corresponding online on-chip debug system is designed in this thesis.The design of the target debug system is based on the pipeline management unit of the processor core which supports breakpoint,single step,reset,register read and write,memory read and write and other normal debug methods.Thanks to the accurate pipeline control technology,the debug system designed in this thesis has the characteristics of low cost and low overhead.For the above designs,corresponding simulation tests and FPGA prototype verifications were performed.The test results show that the target processor can cooperate with the SDR transceiver chip to implement functions such as I/Q calibration and process control.At the same time,the target processor and the core are synthesized separately with the TSMC 40 nm technology.The core area is only 0.026mm2 and the dynamic power consumption is only 3.894?W/MHz,which meets the area power requirements of SDR transceiver chip.Compared to Processors of the same type,this design has certain advantages.