A Research Of Large-capacity FC Switch

Currently,Fibre Channel switches are widely used in storage area network and avionics system.In the storage area network,there is a lot of data needs to be transmitted,and the traditional TCP/IP network is difficult to meet the requirements,and the low latency,high rate,and low error rate of the Fibre Channel protocol can greatly meet the requirements of massive data transmission;In the avionics system,the low-latency,highrate characteristics of the high-performance FC network can well meet the real-time and high-bandwidth requirements of the avionics network.Therefore,Fibre Channel switches play a very important role as the core of storage area network and avionics system.This thesis is based on the project "FC switch design for avionics network",in-depth study of FC protocol,FC switch switching structure and scheduling algorithm,the design and implementation of 48-port FC switch is completed on a single FPGA.Compared with the current commercial switch adopt multiple modules and exchanges data through the backplane bus,the switch of this thesis is based on single-chip FPGA,which can effectively meet the miniaturization,low power consumption,low delay and high reliability of the avionics network core equipment.This thesis provide the technical basis for the next step to realize the FC switch chip for the avionics network.The main work of the thesis includes:(1)Research on the FC protocol,including its hierarchical structure,data frame format,flow control strategy,service type,topology and port type,lays a theoretical foundation for the design of FC switches.(2)The switching structure and input queuing scheduling algorithm of the switch are deeply studied.Based on the iSLIP algorithm,an improved parallel iSLIP scheduling algorithm-MP_iSLIP is proposed.A special cache structure is designed for the MP_iSLIP algorithm,which alleviates the head-blocking problem of the single-FIFO input queue structure to a certain degree.The MP_iSLIP algorithm doesn't need to perform the maximum matching of input and output through multiple iterations,which greatly reduces the complexity of the scheduling algorithm.At the same time,the MP_iSLIP algorithm realizes the scheduling of variable-length data frames,and the delay performance can meet the requirements of the avionics network.Under the premise,the real design of a 48?48 switch can be completely implemented on a single FPGA.Compared with the traditional iSLIP scheduling algorithm,it saves a lot of storage resources and greatly reduces the research and development cost.(3)Based on the MP_iSLIP algorithm,the switch design,simulation and verification are completed on a single FPGA.Firstly,the main modules in the switch: port control module,switch module,monitoring module are introduced in detail.Then,under the Modelsim 10.5 simulation platform,the function simulation is carried out,and finally we combined the Vivado 2017.4 development environment,xigig protocol analyzer and the self-designed switch hardware circuit to complete the function test of the switch,analyzes the integrity of the data frame content,packet loss rate,forward delay and completes the performance evaluation of the switch.