Research And Design Of 76-81 GHz Automotive Radar Transceiver

In recent years,the 76～81 GHz automotive millimeter-wave radar system is being widely researched by scholars at home and abroad.Based on 55-nm CMOS process,a millimeter-wave transceiver chip of 76～81 GHz automotive radar system is studied and designed in this thesis.The main work of this thesis is as follows:（1）A millimeter-wave CMOS quadrature down-mixer operating in 76～81 GHz is designed.To match with former circuits,the down-mixer is a single-ended input.In order to drive the quadrature mixer,a passive power divider is utilized at the input port.The effective transconductance and stability are improved by using neutralizing capacitor technique.A pair of cross-coupled transistors are exploited to bleed dynamic current into mixer core to reduce noise figure while utilizing its negative resistance to improve conversion gain.The post simulation results show that at 25℃、78.5 GHz and TT corner,the mixer reaches its peak conversion gain 8.9 d B and 3 d B bandwidch is about 73.5～83 GHz.The minimum NF in band is 11d B and the maximum NF is 12 d B.The conversion gain ranges from 7.94 d B to 8.9 d B and the IP1d B reaches-2 d Bm in76～81 GHz.（2）A millimeter-wave CMOS tripler operating in 76～81 GHz is designed,which adopts a differential input,differential output and cascode structure.The neutralizing capacitor technique is used in transconductance transistor to improve effective transconductance and isolation.A 3st-harmonic enhancement network is imported into the interstage of cascode to improve 3st harmonic conversion gain and fundamental suppression by first order frequency-selecting.We utilize a transformer as output load to complete second order frequency-selecting and cut off the dc tap of secondary-coil to improve 2st harmonic suppression.The third order frequency-selecting is achieved by a buffer,in which the neutralizing capacitor technique is also used to improve gain and isolation.Besides,the common gate-shorting technique and a new cascode inter-stage network are proposed to improve the gain of buff.The post simulation results show that at 25℃and TT corner,the tripler achieves a 3st conversion gain-5.9～-4.24d B in 76～81 GHz and both of the fundamental and second harmonic suppression are greater than 33 d Bc at TT corner in 76～81 GHz.（3）Other core modules of transceiver in 76～81 GHz are designed,including a low noise ampilifier,a power amplifier and a phase shifter.In LNA design,the source degenerate inductance is used to ahchieve noise reduction and impedance matching.Because phase shifter will influence the overall performance of receiver,we designed phase shifter together with LNA as RF-receiving element.The post simulation results show that at 25℃、78 GHz and TT corner,the RF-receiving element reaches its peak gain 16.4 d B in 76～81 GHz.The minimum NF in band is 8.8 d B and the maximum NF in band is 10.2 d B and the IP1d B of RF-receiving element reaches-15.8 d Bm.The root-means square phase error（（?））is less than 5.4 degree and the root-means square gain error（（?））is less than 0.43 d B.The self-modeling and layout-optimized MOS transistors are used in PA to improve f _MAX.An interdigited structure is adopted in the transistor layout with a source mesh to reduce the impedance.The neutralized capacitance is used to enhance the gain and stability,a common-gate-shorting（CGS）technique is used to boost the maximum stable gain（MSG）,and the inter-stage series and parallel inductance matching technique is used to improve the linearity and efficiency.The post simulation results show that at 25℃,78 GHz and TT corner,the saturated output power reaches 15d Bm,the output power at 1 d B compression point is 12.5 d Bm and the peak PAE is 12%.At 25℃and TT corner,the insertion loss of phase shifter is less than-13 d B in76～81 GHz.The root-means square phase error（（?））is less than 3 degree and the root-means square gain error（（?））is less than 1 d B.（4）The design of a CMOS 76～81 GHz 8TX/8RX FMCW radar transceiver chip is completed.Within 76～81 GHz operating frequency band at TT Corner and 25℃,the post simulated output power of the single channel transmitter reaches 14.6 d Bm.In transmitter array,Peak-to-Peak Ratio is better than 12 d B and Peak-to-Null Ratio is better than 17 d B.At this time,the single channel receiver minimum noise figure reaches 10.2 d B,IP1d B reaches-17 d Bm,the peak conversion gain reaches 22.7 d B.In receiver array,Peak-to-Peak Ratio is better than 12 d B and Peak-to-Null Ratio is better than 22 d B.The total power consumption of the chip is 3.284W.