| With the rapid development of integrated circuit(IC)technology,microcomputer protection based on digital computers and microcomputers has been practically applied and widely developed in power system relay protection.However,while the digital integrated circuit brings convenience to industrial development and social life,it also gradually exposes potential problems.Due to the scaling of the process size and the improvement of the integration level,the circuit operating voltage is continuously reduced,the node capacitance is reduced,and the soft error rate(SER)is caused by the single event effect(SEE)and charge sharing effects has increased.The problem cannot be ignored,and the circuit reliability issues caused by it have attracted more and more attention from industry and researchers.As the most basic timing storage unit in digital integrated circuits,the strength of the latch circuit’s resistance to single event upset(SEU)will directly affect whether the microcomputer protection chip system can correctly process data in the space radiation environment.The technical reliability requirements of power system relay protection pose a serious threat.In this paper,the latch circuits design for SEU tolerance and resilience is studied,and a circuit-level radiation hardening design is proposed.Main tasks as follows:First,the development process of integrated circuits and power system relay protection and the main factors of the rise of soft errors in the process are introduced.Among them,the effects of SEE and charge sharing effect on the data processing of latches are introduced.Secondly,the importance and current status of latch radiation hardening are explained,and representative latch circuits under several existing radiation hardening methods are introduced in turn.Next,the HSPICE simulation tools and commonly used simulation models are introduced in detail.Finally,three radiation hardening designs are proposed for the existing problems.1.Based on the DNCS(2014)latch circuit,adding a weak retainer to the output.When the output and latch circuits are blocked,the high-impedance state of the output logic node cannot hold the data stably for a long time.The principle of error shift term compatibility is used to improve DNCS(2014).The latch circuit proposed a new type of DNCS latch circuit.2.Due to the intensification of the SEE and the charge-sharing effect,the circuit may cause the two storage nodes to logically flip at the same time when the circuit is bombarded by high-energy particles.This paper proposes two single event double nodes upset(DNU)self-restoring latch radiation hardening circuits to solve the above problems,each with advantages in area overhead and self-restoration time.Compared with the existing single event double node upset hardened latch design,the proposed HRLCDRL latch has an area-power-delay product(APDP)reduction of about 40.96%on average.In this paper,node redundancy and other methods are used to study the SEU tolerance and resilient performance of CMOS latch circuits at the current stage.Three latch circuit radiation hardening design schemes are proposed.These schemes not only have a certain degree of comparison with existing radiation-hardened design advantages and also have reference value in the SEU tolerance and resilient hardened design of other memory circuits.Figure [32] table [3] reference [86]... |
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