Design Of SDRAM Controller Based On AHB Bus

With the rapid development of the integrated circuit industry,the in-vehicle Micro Controller Unit(MCU)has become the key technology driving the development of automotive electronics.At the same time,the Central Processing Unit(CPU),the core component of the MCU,has seen a significant increase in its instruction and data processing capabilities,placing higher demands on memory.Synchronous Dynamic Random Memory(SDRAM)has the advantages of large capacity,high speed,small size and low price,which meets the requirements of MCU for memory.However,due to its special operating mechanism and complex control logic,designing a stable SDRAM controller has important application value.This topic originates from the enterprise’s in-vehicle MCU chip research and development project.It is an SDRAM controller suitable for in-vehicle MCU.As an interface module between the Advanced High Performance Bus(AHB)and SDRAM memory,it converts the transmission data of the AHB master device into the communication transactions that conform to the SDRAM memory protocol,meets the memory access timing requirements,and completes the data transmission between the bus master device and the SDRAM memory.This design supports two independently configurable SDRAMs;supports 8-bit,16-bit and 32-bit memory chip;the timing parameters of SDRAM are programmable,and can be flexibly configured for different needs;supports automatic refresh operation,and the refresh rate is programmable;supports self-refresh mode and power-down mode;supports Word,Halfword and Byte access of AHB bus protocol;supports burst transfer of AHB bus protocol,including SINGLE,INCR4,INCR8,INCR16.This paper follows the top-down design principle,and the specific research contents are as follows:Firstly,the related principles of AHB bus protocol and SDRAM memory are studied,which lays a theoretical foundation for the subsequent design of SDRAM controller.Then,according to the demand characteristics of the in-vehicle MCU chip,combined with the module division theory,the architecture design of the controller is completed.According to the results of the module division,the Verilog Hardware Description Language(HDL)is used to complete the design of each module.Register configuration module,synchronization module,control module,input and output modules are implemented successively.The control module as the core module realizes SDRAM initialization,auto-refresh,self-refresh,power-down mode and basic read and write operations.After the basic functions are realized,the design optimizations are carried out: firstly,the First In First Out(FIFO)is used for pre-reading,which improves the read transmission efficiency.Secondly,the specific implementation methods of reducing power consumption in digital integrated circuits are analyzed,and the low power consumption design is carried out by means of latch gated clock.Then,a verification platform based on Universal Verification Methodology(UVM)is built,and the components and specific implementation methods of the verification platform are analyzed in detail.Through the verification of the main function points,the results demonstrate that the controller can achieve the expected planned functions and meet the design requirements.Finally,the collection and analysis of coverage are carried out,and the final coverage results reach 100%,ensuring the completeness of the verification.