IP Design And Implementation Of SM2 Algorithm For IoT Security Chi

The Internet of Things(Io T)is an interconnected network that links disparate devices and objects via communication channels.Its usage has expanded considerably due to the fast-paced advancement of information technology,and it is now an integral component of everyday life.Nevertheless,Io T device security has emerged as a recent and concerning hazard to Cyber defense.Despite achieving some results in safeguarding the security of the Internet of Things(Io T),the current security measures primarily concentrate on the network and system levels,neglecting the security of the Io T devices themselves.Therefore,security chips equipped with national cryptographic algorithm modules have a wide range of potential applications and demand in fields such as the Internet of Things.However,in practical applications,the SM2 algorithm of national cryptography still faces challenges such as complex computation processes and excessive hardware resource consumption.After in-depth research and analysis of the SM2 algorithm,the improvement strategy of this paper is proposed,and the SM2 IP core is realized by hardware and the feasibility of the improvement strategy is verified.On the one hand,it enhances the performance of modular multiplication by optimizing the binary Montgomery algorithm,resulting in a reduction of redundant calculation steps and an improvement in calculation efficiency.Secondly,the Kogge-Stone adder technique is employed to boost the multiplication and accumulation calculation speed and minimize transmission delay.On the other hand,the improved binary modular inverse algorithm can not only complete the modular inverse operation,but also solve the greatest common divisor,which can effectively save the hardware resources required for algorithm execution.Through the improvement of the above two aspects,the overall operation efficiency of the SM2 algorithm is improved.Based on the improved scheme of SM2 algorithm,the SM2 IP core is realized by using FPGA technology.In order to improve the efficiency of SM2 algorithm in hardware implementation,we adopt two improvement methods.Applying bit width optimization technology,this paper reduces hardware resource consumption by defining small bit width and improves running speed by defining large bit width data.Secondly,this paper performs parallel pipeline optimization on the loops appearing in the modular multiplication module and the modular inverse module,so as to further improve the running speed of the algorithm.By using Vivado HLS for simulation and testing,the optimized module is functionally tested and packaged into the IP core,and finally the IP core is instantiated using the software Vivado to evaluate its performance.This paper verifies the digital signature verification results of SM2 IP core from the hardware and software levels respectively,and proves the correctness of the improved scheme.At a clock frequency of 130 MHz,the speed of signature can reach0.31ms/time,and the speed of signature verification can reach 0.39ms/time,with excellent performance.