Low energy phosphorus implantation in silicon

Future ultra large scale integrated (ULSI) devices will require p/n junctions to be formed <20nm below the silicon surface. A route to such junction formation is via low energy ion implantation followed by thermal annealing.; The purpose of this work was to develop current and novel experimental techniques for characterizing shallow implant profiles, more specifically shallow P profiles, as well as to investigate the behaviour of low energy P implants as a possible means to produce ultra shallow junctions.; Low energy (1 to 30keV) P implants in Si(100) have been quantitatively depth profiled by the 31P(alpha, p0)34 S nuclear reaction in combination with ToF-SIMS. This allowed implant qualification as well as P diffusion measurements following rapid thermal annealing for times of 10 to 600 seconds at temperatures from 425°C to 1000°C. Electrical characterization via Hall measurement of the annealed implants has been performed providing carrier density and sheet resistance measurements. A native-oxide stripping technique yielded the first high resolution carrier concentration profiles for low energy P implants in silicon. Activation of up to 100% is demonstrated.; For a subset of the P implants (5keV, phi≥5e14cm-2) a surface a-Si layer is created. During annealing, TA≤600°C, this layer recrystallizes via solid phase epitaxial growth (SPEG). The kinetics of SPEG in the near-surface have been studied using MEIS. P acts as an accelerant of epitaxial Si(100) growth, up to the critical concentration of ∼6e21cm -3. Overall, the results are promising and set a framework for further investigation.