The CTCS-3 Simulation And Testing Platform

With the commercial operation of Wuhan-Guangzhou, Zhengzhou-Xi'an, Shanghai-Nanjing, Nanjing-Hangzhou and other 350km/h high speed lines, the high speed railway in China has entered into a rapid development period. The CTCS-3 train control system has been adopted as the unified technology platform for 350km/h high speed railway in China. Therefore, it is of great significance to establish CTCS-3 simulation and testing platform and to use the advanced simulation technology to assist research and the validation of CTCS-3.This thesis focuses on the research of the modeling and implementation of interlocking simulator, which is an important component of CTCS-3 simulation and testing platform. Considering the complexity of the simulator, this thesis uses Unified Modeling Language (UML) and Rational Unified Process (RUP) to model the system and guide software development. The main work of this thesis is as follows:(1) The functional requirements of interlocking simulator is analyzed and the overall architecture of interlocking simulator is proposed. On this basis, Rational Rose is used to build the visualization models for different stages of system design. The interlocking simulator is analyzed and designed by using the requirement model, static model, dynamic model and architecture model.(2)The basic functions of interlocking simulator are realized, including drawing the station layout, the implementation of the station interlocking core logic, the treatment of route on basis of interlocking logic including route setting, route locking and route release, the reception, analysis and processing of route command, the display of station status and sending of information.(3)Based on HLA/RTI system architecture, the interface communication between interlocking simulator and external equipment is implemented, so as to coordinate the external equipment to complete the basic functionality of CTCS-3 simulation and testing platform.(4)According to the test sequence, the simulator is debugged jointly with external equipment to improve and validate the function of the interlocking simulator.