The Hardware Design And Implementation Of A Rail Flaw Detector

This paper researches the design and implement of Embedded System (ES) Ultrasonic Rail Flaw Detector. The ES is studied intensively based on FPGA and ARM9 as the main hardware. The process of hardware design, implement and debug of ES Ultrasonic Rail Flaw Detector is described. There are 4 main parts in this paper, hardware platform structure design, configuration of ES development environment, FPGA Implementation and Linux driver design.The requirements on the performance of ES are analyzed in this paper, and the hardware platform of ES Ultrasonic Rail Flaw Detector is desiged considering the technical requirements of cooperated company. This ES utilizes ARM as the kernel of hardware and FPGA is used as the main peripheral equipment. At the same time, the theory and process of the major part of the ES are described in this paper. Refering to the relevant information, a basic embedded system development environment is built, including setting up a Linux server, installing and debugging the cross compiler tool chain. Also, the kernel, U-Boot and root file system are designed and JTAG. FPGA is implemented to achieve the functions, shch as high-speed data acquisition, FIR filter, wave form of echo and image display, channel logic control. In the design, using the idea of from top to bottom to fulfill the program, all the modules and functions are designed and simulated step by step. Linux driver is programed by combining the knowledge of Linux driver with the request of hardware. Finally, ES Ultrasonic Rail Flaw Detector is tested and debugged both in hardware and software and all the problems met in the test are solved. The design is accomplished successfully.