Fpga-based Can Controller Design

The question for discussion was about implementing technologies of CAN controller. The goal of the task was to implement CAN controller which accords with CAN 2.0A protocol based on the FPGA device.In the task, FPGA Advantage for HDL Design, Release 5.3, which was developed by Mentor Graphics Corporation was adopted to design the CAN controller. The TOP-DOWN method was adopted in designing CAN controller. according to the method, Block Diagram integrated HDL code, the Block Diagram was applied on higher layers, and the HDL codes was adopted on lowest layers. The CAN controller was verified by Modelsim SE PLUS 5.6a which was developed by Model Technology Incorporated and was embedded in FPGA Advantage. Synthesizing and implementing the CAN controller was carried on ISE6.1.03i which was developed by Xilinx, Inc.Firstly, in this paper, the characteristics of CAN bus and the technologies of designing CAN controller in the world were introduced briefly to help reader to known about the domain I researched into .Secondly, CAN 2.0A protocol was introduced briefly, and the key portion and the difficulties of the protocol were explained in detail.Thirdly, the scheme of the CAN controller was presented by the way of introducing the top block diagrams. The registers accessed by users were introduced in detail. And the design platform, the simulation platform, the chip selected and implementing tools were introduced simply.How I designed the CAN controller was introduced emphatically. The sub-block diagrams of every top block diagram were introduced detailedly, and the key VHDL codes of main sub-block diagrams were presented and analyzed.Emulating the CAN controller functionally is introduced with the emphasis of emulation strategies and methods. The emulation strategies and methods are also fit for the succedent timing simulation.Processes of synthesizing and implementing and verifying CAN controller were...