VLSI Design Of EBCOT In JPEG2000Encoder

JPEG2000still image compression standard has been widely concerned in thefield of image compression, it introduces the discrete wavelet transform andEBCOT algorithms to reach a higher image compression ratio and a more flexibleorganization of the code stream. However, as the algorithm is complex and thecomputing is time-consuming, optimizing the algorithm and realizing EBCOT withVLSI can raise the efficiency of image coding.On the basis of in-depth studying the algorithm of EBCOT, an architecture isproposed for VLSI design. It contains Tier-1encoder and Tier-2encoder,meanwhile the Tier-1encoder is made up of bit-plane encoder and MQ encoder.After further studying on the optimization algorithms and coding principle, wepropose an architecture that contains a pass-parallel bit-plane encoder and adynamic5-stage pipline MQ encoder for Tier-1encoder the key module of EBCOT.To further improve the coding speed, the bit-plane encoder utilizes thestripe-column skip algorithm within every scanning pass.The RTL code of every module in EBCOT is described by Verilog HDLlanguage. And we use the Modelsim simulation tool to build a verification platformwhose input vectors are from OPENJPEG reference software which is also acted as“Gold Model”. The outputs of every module in EBCOT are contrasted to those ofOPENJPEG to do the function verification. Also the stream generated by EBCOT isimported to the JPEG2000decoder to verify whether the stream satisfies thedecoding requirements.At last, we use the ISE and DC tools to synthesize the RTL code of EBCOT.Results show that the working frequency is up to150MHz with hardwareconsumption acceptable. It fully meets the requirements of real-time image coding.