Research And Implementation Of IDWT For High-speed Image Decoder

In the current aerospace remote sensing applications, the satellite image compression systems have high processing speed, which based on FPGA or ASIC(Application Specific Integrated Circuit). While the ground decompression systems typically use software decoding mode and have low processing speed. In order to restore the image in real time, multiple servers usually need to be used for software decoding simultaneously. However, the space and cost of this working method is great. Compared with software decoding, hardware decoding has a higher processing speed and lower power consumption, therefore, the study has great significance on high-speed hardware implementation of image decompression algorithm.JPEG2000 image compression standard algorithm whose core component is the discrete wavelet transform, is one of the best remote sensing image compression methods. For the IDWT(Inverse Discrete Wavelet Transform) in the decoding algorithm, the input data needs to be reorganized. Therefore, it is difficult to implement the parallel processing between columns and rows transform. The current technologies usually adopt the serial manner between columns and rows transform. This manner not only leads to the low processing speed of the JPEG2000 decoding system but also requires large storage resources. Therefore, this paper researches the problem deeply and proposes a high-speed, low-memory and parallel processing structure. The inverse quantization, the IDWT circuit structure and the DDR interface design are also described in detail. Moreover, the high-speed parallel processing problem is mainly solved through overcoming the de-interleaving problem in IDWT.In this paper, we achieve the design through the hardware and the software with the platform of Vivado 2013.3 HLS and Xilinx ISE14.3 integrated development environment. In order to obtain the high accuracy and high speed,we improve the inverse quantization and the IDWT algorithm. Taking 9/7 IDWT of JPEG2000 as an example,We propose a general structure which can be implemented in parallel manner between columns and rows transform and serially among levels. It can support the variable resolution and variable accuracy of image. The proposed VLSI architecture of IDWT is already implemented on Xilinx FPGA Virtex-7 XC7VX485T-2FFG1761 C, and the maximum clock frequency is117MHz. We propose an input cache structure of IDWT. Meanwhile, a scheme of DDR reading and writing control is proposed for the image of 1024×1024×8 bits decompression. Both of them are described via the Verilog language. Also, the circuit structure is invented, which can transfer four input port into one output port for the 1024×1024×8 resolution.In this paper, we focuse on inverse quantization and 9/7 IDWT circuit structure of JPEG2000 compression standard. The IDWT circuit structure includes the basic lifting structure, the column transformation processing unit, the row transformation processing unit and the cache structure between columns and rows transform. Subsequently, we introduce the scheme of wavelet data cache in the DDR and the control of DDR reading and writing for multilevel wavelet transformations.