Design Of High-speed And Large-capacity Storage System Of A Weapon Telemetry System | | Posted on:2014-02-12 | Degree:Master | Type:Thesis | | Country:China | Candidate:Y Q Zhang | Full Text:PDF | | GTID:2232330395992037 | Subject:Measuring and Testing Technology and Instruments | | Abstract/Summary: | PDF Full Text Request | | The high-speed and large-capacity storage system is designed to storage the variousparameters of aircrafts during the flight in order to know its flight conditions and to improveand perfect their function. According to the requirements of the system task, the high-speedand large-capacity storage system is designed to record a large number of data. The storagesystem which has the performances of Anti-high-pressure, resistance to shock and vibrationand anti-electromagnetic interference needs to be designed because of the poor workingconditions of the weapon telemetry storage system. This paper described the overall design ofthe system. The storage system’s function is to receive and store a variety of data which aretransmitted by the encryption unit to storage real-time data of the various parameters of theflight and to transmit to computer by reading interface to obtain the operating parameters ofthe internal device in the aircraft during flight. Xilinx FPGA is selected as the central controlchip and its internal cases of asynchronous FIFO is selected as the buffer module of thereceiving end and the storage side.The LVDS receiver receives10-channel parallel differentialsignals transmitted by the encryption unit, and to convert then to TTL level signals by theconversion chips.8-bit parallel data signals are put in4pieces NAND FLASH chips throughthe control of the FPGA. The invalid blocks of NAND FLASH need to be detected during thestorage. The external EEPROM isn’t used to store the bad block information and the badblock information to be updated, weighing the circuit board size and system task requires. Theinternal RAM of FPGA chip is used to storage FLASH initial bad block informationtemporarily in initialization. The system can meet22.75MByte/s memory speed after thetheoretical calculation and practical test.The pipeline design ideas and ping-pong operationare used during the design of the FLASH memory system. The bottleneck time during theFLASH programming is overcome to improve the system memory speed. Finally, the impactdesign of the storage system is achieved by internal reinforce with epoxy potting and external aluminum buffer. System performances can basically meet the requirements which indicatethe capacity of16GBã€the speed of22.75MByte/s and resistance to shock on testing. | | Keywords/Search Tags: | High-speed, Large-capacity, Storage system, FPGA, FLASH | PDF Full Text Request | Related items |
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