The Research Of Digital Watt-hour Meter On-line Calibration Device Based On FPGA In Intelligent Substation

With the development of the construction of "smart gird" which is presented in China, intelligent substation technology which is considered to be an important part of "smart gird" has obtained widespread concern in academic circles and equipment manufacturers. How to develop substation equipments with a unified interface and a good interoperability between different devices of different manufactures based on IEC61850framework agreement become very important. because of this, researchers need to design the related intelligent electronic equipments based on the understanding of information format and meaning in the intelligent substation process layer. As the important measurement equipment in intelligent substation bay leavel, digital watt-hour meter’ main function is to carry out electric energy measurement by receiving electric quantities in process layer, and provide reference data for the monitoring device and the action of relay protection device in the substation layer. The accuracy of reliability of the power calculation has the important practical significance for the sustained, safe, stable operation of substation.This dissertation is based on the background of digital watt-hour meter calibration device, according to the people’s Republic of China power industry standard of communication networks and systems in substations Part9-1and Part9-2and Altera’ Cyclone Ⅲ Device Handbook device manual, in the basis of research of information processing of Ethernet packet sampling value and its interface communication, study how to realize the function of communication and information processing in FPGA chip, mainly includes three partial contents:The design of data packrt communication is mainly to invoke internal MAC soft-core and configure its register In Quartus Ⅱ software and achieve the function of receiving Ethernet real-time packet in the data link layer, then simulation is performed to verify the design in the timing simulation tool.The design of data packet decoding is mainly to analyse the frame format of IEC61850(-9-1,-9-2,-9-2LE), then using Verilog HDL programming language to extract the voltage, current value and using internal Quartus II built-in Singal Tap Ⅱ logic analyzer probe recording the decoded sampling value and drawing the waveform to verify the design with Matlab software.The design of electric energy metering is mainly to calculate active power by quasi synchronous algorithm and calculate reactive power by the combination of quasi synchronous algorithm and IIR Hilbert transform, then achieve the function by using Verilog HDL programming language.Finally, making use of the laboratory software and equipment, such as:serial debugging assistant, ARM development board, fiber optic transceivers and fiber to verify the design of function and accuracy. The result shows that the configuration of MAC receiving module, decoding and power calculation function module programming are entirely correct, meeting the requirements of the design.