Research And Implementation Of2-Layer Ethernet Switch Based On IEEE1588v2

In the distributed measurement systems, especially power systems, the time synchronization technology has a great significance. IEEE1588standard proposed in2002has solved the partial time synchronization problems in distributed systems. To further improve the accuracy of time synchronization, IEEE1588v2was put forward in2008.In the process of packet forwarding, the packet delay exists not only in the network link, but also in the network devices, such as switches, routers, etc.. There is no specified solution in IEEE1588vl for the residence time inside devices, which would easily lead to the accumulation of errors during synchronization. However, the model of Transparent Clock (TC)is added into IEEE1588v2proposed in2008. The TC can calculate the residence time of Precision Time Protocol (PTP) event packets when coming through traditional network equipments, improving the synchronization accuracy between the master clocks and slave clocks.First of all, the paper describes the research status of the standard after IEEE1588v2was proposed, as well as the research and application status of switches with TC functions. Then it introduces the work principle and process of switches with TC functions. Finally, this paper presents the system design according to the basic functions of the switches and requirements of TCs. The design applies the "CPU+Switch" design idea, which just divides the system into master control and switch modules. Moreover, the master control module selects STM32F407as the control core, while switch module selects the88E6220as the switch core.The design aims at realizing a2-layer Ethernet switch design based on IEEE1588v2standard. The switch not only supports the transmission of ordinary packets, but also the process of PTP event packets, which realizes the model of End to End (E2E) and Peer to Peer (P2P) TCs. The key technic to improve the synchronization accuracy of IEEE1588v2is marking hardware timestamps in the PHY layer. Traditional solutions apply a professional PHY chip named DP83640or Field Programmable Gate Array (FPGA) to produce hardware timestamps. However, both of the two solutions increase the design complicity.This paper applies a professional switch chip supporting IEEE1588v2directly. The switch communicates with CPU and completes the TC functions at the same time. The embedded PHY layer in the switch chip needs to listen to and resolve the PTP event packets. Meanwhile, it needs to mark the arrival and departure time of PTP event packets. CPU needs to communicate with the switch chip to obtain time information of PTP event packets, and add the residence time of the packets to the correction filed of subsequent packets. Accroding to the coordination between master control module and switch moduel, the system can achieve the caculation of residence time for PTP event messages. Additionally, the TC functions are realized.