Design Of High Speed Low Noise LDO With NPN Power Transistor

With the System-on-a-Chip developing to the direction of multi-functional and large-scale integration, the demands for high performance power management units are increasing urgently. As a member of the power management system, low dropout regulator (LDO) becomes more and more widely used because of fast transient response, high power-supply ripple rejection (PSR) and low cost. However, the LDO has some tradeoffs between performence indicators and serveral special design constraints for practical engineering applications. The presented LDO has been used in M-BUS communication chip, high power supply rejection ratio can effectively improve the frequency stability of the internal system clock circuit, fast transient response can guarantee the normal work of the digital circuit, also the output with no reverse leakage characteristics can meet the requirements of the application of the external battery.On the basis of summarizing the existing LDO structures, this thesis analyse the factors which influence the noise from power and transient response characteristics of LDO, and then gives a design which focus on both noise suppression and speed improvement. Power transisitor uses NPN structure to reduce the reverse leakage current of the output and optimize the system transient response; improvement of system power supply noise matching structure and embedded of low pass filter circuit in specific nodes without increasing extra power to improve the high frequency of PSR performance; high speed OTA and slew rate enhancement network further speed up the system's transient response speed; dynamic zero ensures stability of the system in full load range.Simulation and tapeout with Dongbu 0.18?BCD standard process, the result of proposed high PSR fast transient response LDO as follows. This LDO input voltage range is 4.5 to 5.5V, and the output voltage is 3.293V, and the maximum load current is 100mA. When the output voltage is larger than the input voltage, the reverse leakage current is less than 7nA. The PSR achieve -65dB@0Hz and -47dB@100kHz and -50dB@1MHz in heavy load, and the output voltage undershoot and overshoot are 15mV and 13mV with load capacitance 100nF, and the setup time is less then 10?s with the load current changing in 100mA/?s. Compared with the simulation results, the test results have a certain degree of degradation in transient response and PSR.