A General Verification Environment Based On UVM And AXI Interface

With the development of integrated circuit technology,the chip integration is higher and higher.Which is associated with the complexity of the verification was also significantly increased.The verification work already accounts for 70% or more of the IC design,but the chances of success are lower.The traditional verification method relies mainly on directional testing,writing targeted test incentives,If the code,condition coverage requirements are reached,then the verification is sufficient.However,this has already can't satisfy the demand for chip verification.How to improve the quality and efficiency of the chip verification has become an important research direction in the industry.UVM put forward in this paper integrated the essence of many verification methodologies,is a universal verification methodology issued by the industry giant according to the requirements of their own research and development.UVM has the advantages of the automation,flexible,reusable,it represents the latest development of verification technology.This paper deeply analyzes the characteristics of the AXI Interconnector module in the internship project,and summarizes the verification requirements of this module,then put forward a strategy to build the verification platform of AXI Interconnector.By analyzing the characteristics of the module,establish the corresponding behavior model adopting System Verilog,and build transaction level modeling for the content of the transmission.Added each verification component,then carried out simulation and collected coverage report.The report shows that the coverage of single function point reaches 100%,and the overall coverage reaches 93%,which meets the coverage requirement.Then,summarized a set of basic class libraries according to the module characteristics in the project and the future verification environment structure,and use this library as the base library of the subsequent verification component.applicable to the project subsequent validation used as a component of the base class library.Provided a general verification environment than applies to modules and can be reused in system level verification.The verification environment and the corresponding verification strategy raised in this paper has been successfully applied in the subsequent project.The verification environment of AXI interconnector module described in this paper was reused insub-system level verification,the structure of this environment and most of the code can be applied in the subsequent IFFT module,the AC adjustment module,and the Beamforming module.The statistics show that 35% of the code can be reused across following modules,and the cycle of building verification is reduced by 20% while guaranteeing the reliability of verification It ensures the reliability of verification,shortens the cycle of building verification environment,improves flexibility and reusability of verification environment,and saves time and manpower,reduces the cost of the chip verification.