Verification Of PCIe Data Link Layer Based On UVM

With the rapid increase in chip integration and the ever-increasing complexity of chip functions,it is increasingly important to verify the chip to obtain efficient and accurate verification results.UVM(Universal Verification Methodology)verification methodology is a theoretical system dedicated to chip verification.It contains a wealth of features that can speed up the verification process and ensure the efficient completion of chip front-end design.Verification engineers can use UVM to build an efficient and reusable verification environment to verify the function of the chip.As the scale of the chip increases,the communication between different modules is also critical to the improvement of system performance.PCIe(Peripheral Component Interconnect Express)high-speed peripheral interconnection standard is widely used in consumer electronics and servers.The main function is to increase the transmission speed between the processor,memory and peripheral devices,and improve the accuracy of data transmission.The main function of PCIe’s data link layer is to provide protection for the entire data transmission process.It includes Ack / Nak protocol functions,power management functions,and flow control functions.When data transmission errors and received data packets are retransmitted in error,PCIe can use the above functions to restore the state of the device in time and ensure the correct transmission of data.These features make PCIe quickly popular in the industry.This thesis is based on the study of the basic principles of PCIe,combined with the functions of PCIe in actual work,using the UVM verification methodology to establish a verification environment to perform functional verification of PCIe 2.0,and constructing a UVM verification platform,using System Verilog language to write verification use cases.Based on the research of the functions and communication protocols within each level of 2.0,the advanced mechanism of sequence and factory of UVM is used to perform functional verification on the data link layer in PCIe 2.0 using directional excitation and random excitation based on coverage.The key is to check for possible test incentives and inappropriate random constraints in the verification code,use the Perl scripting language to control the operation of the verification use cases and perform regression testing,to achieve automatic collection coverage,and at the same time print the wrong use case information,and then to the failed use cases Analyze and debug until all configurations in the test sequence are executed once and the code coverage is counted using script commands.After running a large number of test cases,the functional coverage rate reached 100% and the code coverage rate reached 88%.The results obtained after analysis and research met the requirements of functional verification and reached the expected goal.This thesis aims at the shortcomings of the existing research on the data link layer of PCIe and the weak links in the realization of UVM.Study the format of the PCIe packet and the entire data processing flow of the system in detail,especially for the mechanism introduced by the data link layer to achieve various functions Conduct in-depth research.Based on the previous research,combined with actual engineering,some efficient and reusable methods are proposed for the construction of the UVM verification environment,which can reduce the workload of the verification personnel and help the verification personnel build a highly efficient and highly portable verification environment.Finally,I made some thoughts on the future development direction of PCIe and UVM.The overall work of this article has laid a certain foundation for the subsequent technical research.