UVM-based Automatic Signature And Verification System

With the continuous development of the information society,the application field of communication technology is constantly expanding,resulting in many data and information security problems,including but not limited to the integrity data and unforgeability problems.Therefore,digital signature verification technology is widely used in the field of information security.A typical application is the signature verification of data stream between FPGA(Field Programmable Gate Array)chips and software tools.With the explosive growth of data information,it is urgent to improve the efficiency of signature verification,and at the same time to ensure the functional correctness of the algorithm implemented by hardware methods in the FPGA chip.Therefore,how to implement an automatic signature verification system from the perspective of a verification engineer has become a new topic.Simulation software tools and UVM(Universal Verification Methodology)verification methodology are used to implement a system,which can automate signature verification in this project.The automatic system can be divided into two parts: data stream signature verification and public key verification.The part of data stream signature verification realizes the signature and verification of the data to be signed,ensuring data integrity and functional correctness of SHAKE256 algorithm and RSA algorithm.The part of public key verification is used to ensure the correctness of public key transmission from software to chip and the functional correctness of SHA3-384 algorithm.The hash and the signature verification algorithm model are implemented by System Verilog language.In the UVM environment,the data stream that would be signed and verified is sent into the algorithm and the algorithm model.If a text file of verified data stream is successfully output,the signature verification is successful.In the software tool,the data stream to be signed is driven into the SHAKE256 algorithm model in the form of text file obtaining the digest of the data stream to be signed,and then the digest is sent into the RSA signature algorithm model obtaining the data stream signature.The signature information and the data stream to be verified are respectively transmitted from the software tool side to the FPGA chip side,and the digest of data stream is calculated by the RSA verification algorithm and the SHAKE256 algorithm.To facilitate UVM verification methodology,the RSA verification algorithm and SHAKE256 algorithm are encapsulated as DUT(Design Under Test),and the RSA verification algorithm model is introduced and instantiated into the reference model component.If the digest value of RSA verification algorithm is equal to the digest value of SHAKE256 algorithm and the digest value of algorithm model,it can be determined that the data stream signature verification is passed.To ensure the correctness of the public key during transmission,it is necessary to drive the public key to the SHA3-384 algorithm and algorithm model to obtain the public key digest.If the digests of public key are consistent,the public key verification is passed.Finally,the verification data stream file is automatically output.Compared with the algorithm model implemented by C language in the previous solution,the speed of the hash and signature verification algorithm model implemented by System Verilog is about 10% faster in the environment.And the RSA algorithm model is implemented based on the high radix carry-preserving Montgomery algorithm,which makes the performance of the RSA algorithm even better.It takes about 50.1 seconds to use automatic signature verification system for hashing,signature and other operations,but it takes about 55 seconds for the same data by C language.In addition,the time required to manually drive the data to the C language algorithm model is uncontrollable but will be much longer than the automation process.