Research And Design Of A Low Power Capless Low Dropout Regulator

As a part of power management circuit,low dropout regulator is more and more widely applied to portable devices,and step forward to chip integration.Due to the characteristics of easy integration and simple application,Capless LDO became as the first choice for many applications.Compared with the traditional LDO, Capless LDO has disadvantages in stability and transient response,they are very difficult problems to solve.Aiming at two shortcoming of Capless LDO:bad stability when load current is small and relatively slow transient response speed.This paper proposed a solution to enhance transient response speed as well as stability.Detailed work is the design of LDO using SMIC0.13μm CMOS process,the LDO must give 100 mA current to digital circuit load,at the same time,it must have very low dropout voltage、high PSRR performance、low power dissipation 、 good noise performance and good transient response ability.Among all components,band gap and error amplifier are crucial circuit in this design,they directly determine the performance of LDO.In order to make the band gap to work under 1.4V power supply and keep high PSRR performance,this paper analyses the drawbacks of classical band gap structure,and make some change,then complete the design goal.At the same time,the error amplifier uses multistage amplifier to ensure enough loop gain,applying Miller compensation method to make the loop stable.Newly designed transient response enhancement circuit can make LDO work fast.The LDO(including bang gap design) is finished in SMIC0.13μm CMOS process and verified using spice program.Simulation result shows:when the voltage of the power source is 1.4V,this LDO can produce 1.2V output voltage,it can drive 0.2mA~100mA current to load,the dropout voltage is smaller than 200mVPSRR(@DC)is, less than-58 dB,PSRR(@100kHz)is less than-18 dB.Quiescent Current is less than 75μA,setting time is less than 2μs,overshoot voltage is less than 72 mV.