Low power capacitively driven on-chip wires with pulse width modulation

This thesis presents a low power design for driving on-chip wires. The system modulates 3-bit input data into a single signal and demodulates it after transmission on a long on-chip wire. Instead of using conventional repeaters, this work drives the on-chip wire with a series coupling capacitor, which offers a reduced voltage swing on the wire for low energy. The capacitor reduces the driven load, allowing for smaller drivers. A self-biased amplifier at the receiver end with an unbalanced precharge technique amplifies a differential input signal and recreates the modulated signal. Simulations of an implementation in a 0.25 mum CMOS process show a decrease in the worst case power of 7% over a full-swing pulse width modulation system driving long wires at 10 Mbps throughput and 1V Vdd. Power savings for wire lengths reach 5%,7%, 7% and 9% for 7.89 mm, 9.2 mm, 10.5 mm and 11.8 mm, respectively.