The Research And Design Of Inverter-Based Ultra-Fast Transient Response LDO

With the rapid development of modern science and technology,concepts such as 5G,Internet of Things,and artificial intelligence have been proposed one after another,and gradually entered into people's daily life.The new generation of electronic products derived from them,such as smart homes and smart wearable make people's demand for electronic products increasingly strong.Power is the heart of electronic products.Any electronic product cannot be separated from the power supply.The use of an efficient power management system can not only reduce the power consumption of electronic devices and extend their service life,but also enable electronic devices to perform better.LDO(Low Dropout Regulator)is an important member of power management system.It has the advantages of low ripple,low power consumption and fast transient response,etc.It is widely used in various electronic products.Compared with the traditional LDO,the LDO without off-chip capacitor has poor transient response performance due to the lack of large off-chip capacitor,and has a large overshoot voltage and undershoot voltage.This paper focuses on optimizing the transient response of LDO and reducing the power consumption of LDO.By inserting a two-stage inverter as a two-stage small gain stage in the classic LDO circuit structure,the loop gain can be increased in the steady state,thereby reducing the line regulation and the load regulation;In the transient state,it is provided for the PMOS power transistor a larger charge current or discharge current to optimize the transient response.Due to the addition of two small gain stages,the loop stability is affected.In this paper,Miller compensation is used to improve the stability of the loop.Based on the proposed optimization scheme,this paper uses 65 nm process to design a LDO with fast transient response and low power consumption.And carry out PVT(Process/Voltage/Temperature)simulation on the designed circuit to verify the performance of the circuit under different process angles,voltages and temperatures.Completed the layout design of the designed LDO and conducted post-simulation.The post-simulation results show that the designed LDO can work normally in both scenarios with and without off-chip capacitors.When the input voltage range is between 0.7V and 0.9V,the output voltage can be stabilized at 0.5V,the minimum dropout is 200 mV,the load current range is 1mA-100 mA,the quiescent current of the core circuit is about 10?A;the load regulation is only 0.3?V / mA,the line regulation is only 1.08 mV / V.Without the off-chip capacitor,the output voltage changes by only 5.36 mV when the load changes from a light load of 1mA to a heavy load of 100 mA within 100 ns.When the load transient change speed is faster,and the change time is 10 ns,it is difficult for the LDO without off-chip capacitor to continue to ensure small voltage changes.At this time,a 1?F off-chip capacitor can be connected to the output to further improve the transient response.When there is an off-chip capacitor,the output voltage changes to 58.3mV when the load changes from a light load of 1mA to a heavy load of 100 mA within 10 ns.